`include "macro.v"
module SEXT (
    input wire [2:0] sext_op,
    input wire [24:0] din,
    output reg [31:0] ext
);

wire sign = din[24];

always @(*) begin
    case (sext_op)
        `SEXT_I: ext = {{20{sign}},din[24:13]};
        `SEXT_S: ext = {{20{sign}},din[24:18],din[4:0]};
        `SEXT_B: ext = {{19{sign}},din[24],din[0],din[23:18],din[4:1],1'b0};
        `SEXT_J: ext = {{11{sign}},din[24],din[12:5],din[13],din[23:14],1'b0};
        `SEXT_U: ext = {din[24:5],12'b0};
        default: ext = 32'b0;
    endcase
end

endmodule